1. Field of the Invention
This invention relates to computing systems, and more particularly, to efficiently addressing dies in a three-dimensional stacked integrated circuit.
2. Description of the Relevant Art
As both semiconductor manufacturing processes advance and on-die geometric dimensions reduce, semiconductor chips provide more functionality and performance. However, design issues still arise with modern techniques in processing and integrated circuit design that may limit potential benefits. One issue is that interconnect delays continue to increase per unit length in successive generations of two-dimensional planar layout chips. Also, high electrical impedance between individual chips increases latency. In addition, signals that traverse off-chip to another die may significantly increase power consumption for these signals (e.g., by 10 to 100 times) due to the increased parasitic capacitance on these longer signal routes.
Progress has been made in three-dimensional integrated circuits (3D ICs) that utilize die-stacking technology to allow two or more layers of active electronic components to be integrated both vertically and horizontally into a single circuit. Die-stacking technology is a fabrication process that enables the physical stacking of multiple separate pieces of silicon (integrated chips) together in a same package with high-bandwidth and low-latency interconnects. The 3D packaging saves space by stacking separate chips in a single package and provide high-density, low-capacitance interconnects compared to traditional two-dimensional planar wire-bonds.
Similar to other microelectronic products, the 3D packaging is tested for manufacturing and design defects. A test architecture, such as the Joint Test Action Group (JTAG) boundary scan architecture, may be used to transport test data and control signals. In a post-bond stack situation, the external input/output (I/O) signals are typically located on the bottom die. Therefore, the test vectors and responses for each of the middle and top dies may need propagate through all dies below it.
Unique addresses may be used to distinguish one die from another within the 3D package during testing. However, due to different product configurations and the fact a given die may be re-used in different configurations, poses difficulties. Additionally, different dies within a 3D package may have their own technologies and design architecture approaches and die enumeration method for testing that assigns, or enumerates, unique addresses cannot modify these approaches. Preferably, the die enumeration method consistently provides unique addresses despite configuration changes both horizontally and vertically. Current die enumeration methods are not sufficiently adaptive to handle these characteristics.
In view of the above, efficient methods and systems for efficiently addressing dies in a three-dimensional stacked integrated circuit are desired.